The present disclosure relates to a semiconductor device, and more particularly, to a memory semiconductor device and a method of operating the same.
In the memory semiconductor technology field, data distribution may affect speed, life and reliability of product. In particular, in a multi-level cell (MLC) in which one memory cell can have one state of multiple data states (e.g., voltage levels), data distribution is an important factor because of the importance of separation between data states. A reduction in the voltage margin separating voltage levels in the MLC that yield the desired bit information can result in the possibility of more errors.
As the integration of memory semiconductors increases, control of such data distribution is becoming increasingly difficult. Regarding technology for suppressing short channel effect, methods of reducing an impurity concentration of source/drain regions of metal-oxide-semiconductor field-effect transistors (MOSFETs) have been suggested. However, those methods can affect data distribution since impurity concentrations of one MLC can affect voltage levels of adjacent MLCs in memory strings of a memory cell array.